Photonic Wafer-Level IntEgration PAckaging and Test Processes

PhotonicLEAP will develop a disruptive wafer-level PIC module integration, packaging and test technology which can be scaled from low to very large volumes. PhotonicLEAP will use this disruptive technology to produce a revolutionary Surface Mount Technology (SMT) PIC package, which for the first time incorporates multiple optical and electrical connections. SMT is the most widely used, cost-effective and standardised package in the electronics world and PhotonicLEAP’s standardised SMT approach is set to follow, becoming a new global standard for costeffective PIC packaging and high-throughput PIC testing. PhotonicLEAP will also develop standardised packaging design rules formalised into a Process Design Kit (PDK), providing users with easy access to the project technology through Open Access and commercial PIC design software tools.

PhotonicLEAP’s novel wafer-level PIC packaging and test technology will be used to produce a revolutionary Surface Mount Technology (SMT) PIC package, combining breakthroughs in advanced materials, innovations in optical and electrical packaging and ultra-fast wafer-level assembly processes giving > 10 times reduction in PIC production costs.

This project has received funding from the European Union’s Horizon 2020 research and innovation program Grant Agreement N°101016738, in Public Private Partnership with Photonics 21 ( Copyright © 2021 PhotonicLEAP All rights reserved